1. Field of the Invention
The present invention relates to a data bus conversion apparatus for use in various bus systems. More particularly, the present invention relates to a data bus width conversion apparatus which allows bus access between a CPU (host system) and its peripheral devices which have different data bus widths.
2. Description of the Related Art
When a CPU having a data bus width of M bits (M is a positive integer) tries to access an LSI (peripheral device) having a data bus width of N bits (N is a positive integer) which may be different from M, a data bus width conversion apparatus for resizing (changing) the data bus width is required. Note that M may be equal to N.
Japanese Laid-Open Publication No. 4-76890 discloses a conventional data bus width conversion apparatus comprising a memory cell array section for resizing a data bus width, in which the memory cell array section is used as a cache memory or a local memory (page 579, FIG. 1).
Japanese Laid-Open Publication No. 3-97340 (pages 256–257, FIGS. 1 and 2) and Japanese Laid-Open Publication No. 5-242016 (page 3, FIG. 1) disclose a conventional data bus width conversion apparatus comprising a latch circuit and an output control circuit between a data bus having a data bus width of M bits and a data bus having a data bus width of N bits in order to resize a data bus width.
However, in the above-described conventional data bus width conversion apparatuses, the number of access operations by a CPU required for transfer of N-bit data from the CPU to an LSI, the wiring pattern of connection between the CPU and the LSI, and the like, are fixed in hardware in order to resize a data bus width. Therefore, it is difficult to apply the conventional apparatuses to various bus systems.
For example, the data bus widths of conventional CPUs (host system) are set to a multiple of 8 bits (8 bits, 16 bits, 32 bits, etc.) in accordance with customary practice. However, a data bus width of 3 bits (18 bits, 24 bits, etc.) may be used in a number of display apparatuses, such as a liquid crystal module and the like. This is because display data for a display apparatus is composed of three color elements RED, GREEN and BLUE. If these three color elements have the same bit width, a data bus width has a multiple of 3 bits.
For example, it is assumed that a liquid crystal module having a data bus width of 18 bits is connected to a CPU having a data bus width of 8 bits. It is necessary to transfer all of 18-bit data from the CPU to the liquid crystal module in order to maximally exploit the display performance of the liquid crystal module. In this case, since the data bus width of the CPU is 8 bits, it is necessary to divide 18-bit data into at least three in order to transfer the data from the CPU to the liquid crystal module. For 18-bit data, there are various division patterns, such as 8-8-2, 6-6-6, 5-6-7, etc.
The minimum number of divisions for 18-bit data is three as described above. Alternatively, the number of divisions may be more than three (i.e., (the number of divisions)≧3) because of a particular CPU's structure, logic, or the like.
In conventional data bus width conversion apparatuses, the division pattern and the number of divisions of 18-bit data are fixed in hardware. Thus, when the above-described CPU interface is constructed by an LSI, the number of divisions and the division pattern are fixed in the LSI design. Therefore, the type of an LSI available for a CPU is limited and a CPU requires a software processing or the like.